CR001k4 读写模块-北京华闰得科技有限公司手机版

详细介绍

Operational and Physical Characteristics

Parameters	Description	Photo
Read Range	8-12cm
Dimensions	26.5mm(L)x16.5mm(H)x6.9mm(W)
Frequency	125kHz
Card Format	EM 4001 or compatible
Encoding	Manchester 64-bit, modules 64
Power Requirement	3VDC @ 30mA nominal
Voltage Supply Range	+2.7V through +3.6VDC

　Pin Description & Output Data Formats

Pin No.	Description	CR001B-K4-2 (ASCII)	CR001B-K4-W2(Wiegand26)
Pin 1	To External Antenna	Antenna	Antenna
Pin 2	To External Antenna(L:680uH)	Antenna	Antenna
Pin 3	Con	Strap to Vcc(High Volts)	Strap to Vcc(High Volts)
Pin 4	BEEPER/LED Drive	2.7kHz Logic	2.7kHz Logic
Pin 5	DATA0	CMOS Data Output(TX)	Zero Output
Pin 6	DATA1	TTL Data（inverted）Output	One Output
Pin 7	CS	CS	HOLD Output
Pin 8	Zero Volts Or Ground	GND 0V	GND 0V
Pin 9	DC Voltage Supply(Vcc)	+2.7V through 3.6VDC	+2.7V through 3.6VDC

　DATA FORMATS

CR001B-K4-2 Output Data Structure – ASCII(RS232.TTL)9600,N,8,1

STX (02H)

DATA(10 ASCII)

CHECK SUM (2 ASCII)

ETX (03H)

[The 1byte (2 ASCII charaters) Check sum is the “Exclusive OR” of the 5 hex bytes(10 ASCII) Data characters.] For Example:DATA : 62H E3H 08H 6CH EDH, Check Sum: (62H) XOR (E3H) XOR (08H) XOR (6CH) XOR (EDH)=08H, Output: 0X02 0X36 0X32 0X45 0X33 0X30 0X38 0X36 0X43 0X45 0X440X0D 0X0A 0X03

　CR001B-K4-W2 Output Data Structure–Wiegａnd 26 bit

1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26
P(1)	E	E	E	E	E	E	E	E	E	E	E	E	O	O	O	O	O	O	O	O	O	O	O	O	P(2)
EVEN Parity(E)													ODD Parity(O)

　P(1):Parity Start Bit, 2-13 bit EVEN Parity bit
P(2):Parity Stop Bit, 14-26 bit ODD Parity bit

　Wiegａnd Output Structure

SYMBOL	Parameter	Limits Min.	Limits Max.	Type	UNITS
THD	Hold Start data read delay time	0.5	2	0.55	mS
TDW	Data Pulse width time	20	100	50	μS
TIW	Data Pulse interval time	0.2	4	1.1	mS
TSN	Data Send delay time	5	-	80	mS
TCS	Hold and Start read time	40	120	100	mS
TA	Total scan time	100	-	-	mS

产品简介

详细介绍